1. Field of the Invention
The invention relates generally to random access memories. In particular, the invention relates to a random access memory, any location of which can be simultaneously read by a multiplicity of ports.
2. Background Art
There exists a need in some microprocessor applications to have high speed registers in which each register can be separately addressable from a multiplicity of data-in ports for a write and separately addressable from a multiplicity of data-out ports for a read. The use of multi-port memories is old in the art. In such a multi-port memory, allowance must be made for the fact that the same memory location may be simultaneously accessed by more than one of the data-out or read ports. That is, in a given read cycle, the same memory cell may be required to control the output circuitry for more than one port. Bit lines are typically precharged before reading. In this situation, the memory cell must obviously have the current sinking capability for simultaneously transferring its data signal by discharging more than one output port. This problem is generically known as fan-out. Conceptually, increased fan-out can be accommodated by increasing the size of the output transistors in the individual memory cells so that they can discharge multiple bit lines. The primary difficulty with this approach of increasing the size of the discharge transistors is that the transistors need to be associated with each of the memory cells and the size of the transistors increase with their current discharging capability. As a result, the resultant memory chip may become excessively large. Furthermore, response times are increased at the same time that the current sinking levels are increased. Hence, the memory is both unacceptably large and too slow. Bernstein and Furman in a series of patent applications, Ser. No. 474,071, filed Mar. 10, 1983 (U.S. Pat. No. 4,535,428, issued Aug. 13, 1985), Ser. No. 499,729, filed May 31, 1983 (U.S. Pat. No. 4,577,292; issued Mar. 18, 1986) and Ser. No. 499,730, filed May 31, 1983 now U.S. Pat. No. 4,616,347 issued Oct. 7, 1986 have described an alternative approach. The concept is presented schematically in FIG. 1 for a plurality of individual memory cells 12, of which only three are shown in the figure. Furthermore, the figure does not show the parallel nature of a register memory in which multiple cells are accessed in parallel to provide a multi-word. Finally, FIG. 1 does not show the circuitry associated with the writing of the memory cells 12 but is concerned only with the reading of the cells. The illustrated memory system has three read ports that read respective memory cells 12 as indicated by respective addresses P1, P2 and P3. Address decoders 14, 16 and 18 receive the address signals P1, P2 and P3 and, after decoding the addresses, activate respective word lines 20 for coupling the contents of the selected memory cells 12 to bit lines 22. In a three-port system, there would be 3 bit lines 22, each generally corresponding to a particular port. The address P1 would be the address of the memory cell 12 to be coupled to the first port. Similarly P2 is associated with the second port and P3 with the third port.
The problem arises when two or more of the addresses P1, P2 and P3 are equal so that one of the memory cells 12 is expected to discharge two or more of the bit lines 22. A better solution than increasing the size of the discharge transistors in the memory cells 12 is to instead compare the three addresses P1, P2 and P3 in comparators 24, 26 and 28. If the two addresses P1 and P2 are equal, then the decoder 16 for the second address P2 is disabled. Similarly, if the addresses P1 and P3 are equal or if the addresses P2 and P3 are equal, then the decoder 18 for the third address P3 is disabled. As a result, a particular memory cell 12 is selected by only one of the decoders 14, 16 and 18 regardless of the equality of the addresses P1, P2 and P3. Furthermore, if the addresses are ordered in a rising sequence from P1 to P3, then the lower order bit lines 12 are favored.
The task then remains in the case in which some of the addresses are equal to inhibit the respective port from reading what is normally its associated line but instead to transfer the data from one bit line 22 to another port. This function is performed by the inhibit and transfer circuits 30, 32 and 34. For instance, if P1=P2=P3, then both of the decoders 16 and 18 would be disabled and the selected memory cell 12 would be read only from a single bit line 22. However, the single bit line would then be coupled to all 3 read ports through the three inhibit and transfer circuits 30, 32 and 34. The advantage of this approach is that at no time does any memory cell 12 need to discharge more than one bit line.
The transfer and inhibit circuits described in the above three patent applications are disadvantageous for a number of reasons. They tend to separate the two functions of inhibiting and transferring into two separate circuits. As a result, the circuits are excessively complex. Furthermore, in all three applications, differential bit lines are being used. In the read state, one of the differential bit lines is high while the other is low. It is preferred that the number of lines be reduced by using single ended reads from the memory cell. In this case, it is further advantageous to precharge the bit lines so that they can be selectively discharged by the memory cell to which they are connected. None of the applications discloses how the bit lines would be precharged.